1. Field of the Invention
This invention relates to ferroelectric memories, and more particularly to such a memory utilizing such ferroelectric field effect transistors and methods of operating such transistors and memories.
2. Statement of the Problem
It has been known since at least the 1950""s that if a practical ferroelectric memory could be made, it would provide a fast, dense, non-volatile memory that could be operated at relatively low voltages. See Orlando Auciello et al., xe2x80x9cThe Physics of Ferroelectric Memoriesxe2x80x9d, Physics Today, July 1998, pp. 22-27. The principal type of ferroelectric memory being explored today is the non-volatile ferroelectric random access memory or NVFRAM. Ibid. A disadvantage of the NVFRAM is that, in the process of reading it, the information it holds is destroyed and, therefore, the read function must be followed by a rewrite function. However, it has been postulated for at least 40 years that it may be possible to design a memory in which the memory element is a ferroelectric field effect transistor (FET), which memory could be non-destructively read. See Shu-Yau Wu, xe2x80x9cA New Ferroelectric Memory Device, Metal-Ferroelectric-Semiconductor Transistorxe2x80x9d, IEEE Transactions On Electron Devices, pp. 499-504, August 1974; S. Y. Wu, xe2x80x9cMemory Retention and Switching Behavior Of Metal-Ferroelectric-Semiconductor Transistorsxe2x80x9d, Ferroelectrics, Vol. 11, pp. 379-383, 1976; and J. R. Scott, C. A. Paz De Araujo, and L. D. McMillan, xe2x80x9cIntegrated Ferroelectricsxe2x80x9d, Condensed Matter News, Vol. 1, No. 3, pp. 15-20, 1992. Because the ferroelectric memory effect measured in the early devices of Wu was only a temporary, single state effect rather than a long lived two-state effect, it is now believed that this effect was charge injection effect rather than an effect due to ferroelectric switching. However, a metal-ferroelectric-insulator-semiconductor FET device, i.e. a MFISFET, has recently been reported that appears to show true ferroelectric memory behavior. See Tadahiko Hirai, et al., xe2x80x9cFormation of Metal/Ferroelectric/Insulator/Semiconductor Structure With A CeO2 Buffer Layerxe2x80x9d, Japan Journal of Applied Physics, Vol. 33, Part I, No. 9B, pp. 5219-5222, September 1994; Tadahiko Hirai et al., xe2x80x9cCharacterization of Metal/Ferroelectric/Insulator/Semiconductor Structure With A CeO2 Buffer Layerxe2x80x9d, Japan Journal of Applied Physics, Vol.34, Part I, No. 8A, pp. 4163-4166, August 1995; Yong Tae Kim et al., xe2x80x9cMemory Window of Pt/SrBi2Ta2O9/CeO2/SiO2/Si Structure For Metal Ferroelectric Insulator Semiconductor Field Effect Transistorxe2x80x9d, Applied Physics Letters, Vol.71 No. 24, pp. 3507-3509, Dec. 15, 1997; and U.S. Pat. No. 5,744,374 issued Apr. 28, 1998 to Jong Moon.
To make a memory requires not only a memory element, but also a means for addressing a large number of memory elements. Initially, it was believed that a ferroelectric memory element might be addressed by a simple array of rows and columns of conductors. A ferroelectric memory element, it was thought, could be located at each of the junctures of the array and addressed by applying a voltage to the conductors for the corresponding row and column. It was believed that if the voltage on each conductor was less than the threshold voltage for ferroelectric switching (coercive voltage) and the voltage difference between the conductors was greater than the coercive voltage, then only the selected cell would be written to or read, and the other cells would remain unchanged. However, it was found that this did not work because the neighboring unselected cells were disturbed by the voltages on the address lines. Thus, a switch was added between one of the address lines and each ferroelectric memory element. See U.S. Pat. No.2,876,436 issued Mar. 3, 1959 to J. R. Anderson and U.S. Pat. No. 4,873,664 issued Oct. 10, 1989 to S. Sheffield Eaton, Jr. If the switch is a transistor as in the latter patent, the memory assumes a memory address architecture essentially the same as that of a conventional DRAM. However, when applied to a ferroelectric memory, even this architecture disturbed the memory cells attached to the same plate line as the addressed cell. That is, it has been found that ferroelectric materials do not have a sharp coercive threshold voltage, but rather even a small voltage will cause the ferroelectric to partially switch and, therefore, the repetitive application of small disturb voltages, such as occur in a conventional memory array, eventually causes the change or loss of a memory state. Therefore, a more complex architecture was proposed to overcome this disturb. See, for example, U.S. Pat. No. 4,888,733 issued Dec. 19, 1989 to Kenneth J. Mobley.
The above address schemes are all for a NVFRAM; that is, a memory utilizing a ferroelectric capacitor as a memory element, rather than for a memory utilizing a ferroelectric FET. A number of address architectures have been disclosed up to now for a memory in which the memory element is a ferroelectric FET. U.S. Pat. No. 5,523,964 issued Jun. 4, 1996 to McMillan et al., discloses a relatively complex addressing architecture, utilizing five transistors in each memory cell in addition to the ferroelectric FET. This complexity is incorporate to, like the Mobley et al. architecture, to avoid the disturb problem. Such complex architecture results in a memory that is much less dense and slower than, for example, a conventional DRAM. An architecture that uses one ferroelectric FET per memory cell has been proposed, but has not been implemented because it cannot be read properly if three neighboring cells all are in the conducting logic state. See, U.S. Pat. No. 5,449,935 issued to Takashi Nakamura on Sep. 12, 1995, col. 3, line 56-col. 4, line 15. Another such one-FET-per-memory cell design has been proposed in U.S. Pat. No. 5,768,185 issued to Takashi Nakamura and Yuichi Nakao on Jun. 16, 1998. However, during reading a voltage of 3 volts to 5 volts is applied to the word line while the ground or zero volts is applied to the bit line. While this is not enough to switch the ferroelectric in a single read cycle, as indicated above, it is now known that successive pulses of this magnitude, such as occur in a memory in the normal process of reading, can disturb the ferroelectric state. In addition, since the bit line is connected to the source and substrate and the word line is connected to the gate, it the WLn and BLm+1 signals are not exactly synchronized, the erase process of one cell will disturb the next. Under manufacturing specifications that are practically feasible, such exact synchronization is difficult to achieve in all cells. Therefore, in a commercial product there will short disturb voltages during the erase cycle also. Further, with this architecture, it is not possible to write a byte at a time, which is a much faster way of reading in a ferroelectric FET. Thus, it appears that the fact that the ferroelectric material does not have a sharp coercive field threshold and can be switched by repetitive applications of a small voltage has made several of the original objectives of research into ferroelectric memories unattainable. It would, therefore, be highly desirable to provide an architecture and method for addressing a ferroelectric memory, particularly a ferroelectric FET structure and method of making the structure, that was relatively simple and, at the same time, avoided the problems in the prior art, such as the disturb problem.
The invention solves the above problem by providing a method and apparatus for addressing a ferroelectric memory in which each memory cell preferably contains only the ferroelectric memory element, e.g., a ferroelectric FET.
In one aspect the invention comprises placing the source/drains of the non-selected memory cells n a high resistance or open state.
Another aspect of the invention comprises placing the gates of both the selected and non-selected cells in a high resistance or open state during the read cycle.
Another aspect of the invention comprises placing the source of the non-selected cells in a high resistance or open state during the read cycle.
Another aspect of the invention comprises placing the source of each memory cell in the selected row in a different electronic state than the sources of the cells in the non-selected cells during the read cycle.
A further aspect of the invention is to write an entire byte of cells at the same time, thus greatly increasing the speed of the write process.
The architecture of the memory is simple: one electrical element of each FET is connected to a row select line, and another electrical element of each FET is connected to a column select line. Preferably, there are two column select lines, one for the write function and one for the read function. Preferably, both column select lines are parallel, so the fact that there are two column lines adds little to the memory density.
The memory is preferably written to by setting either all the cells or a row of cells to a first logic state, and then placing the row select line of the selected memory cell or cells in a first electronic state, while the non-selected row select lines are placed in a second electronic state different than the state of the selected row line. Then any cell in any column of the selected row can be written to a second logic state different than the first logic state by placing the column line in the opposite logic state, or can be left in the first logic state by placing the column line in the same logic state as the row select line. Preferably, the first and second electronic states are voltage states. Preferably, all the column lines are selected at the same time, so that a byte of memory is written to simultaneously.
The memory is read by placing the column select line of the selected memory cell in a first electronic state and the row select line of the selected memory cell in a second electronic state different from said first electronic state, while the row select lines of the non-selected cells are placed in a third electronic state, which is preferably a high resistance state. The current in the column line then indicates the state of the selected cell. Preferably, all the columns are selected, so that a byte of memory is read simultaneously.
The probability of a disturb is significantly decreased by a FET structure in which no portion of the source/drains underlie the gate. A self-aligned process of making the FET automatically creates this structure, thus greatly lowering the probability of disturbing non-selected FETs during the write process, and disturbing any FETs during the read process.
The invention provides ferroelectric memory comprising a plurality of memory cells each containing a ferroelectric FET, each of the ferroelectric FETs having a source/drain and a gate, wherein no portion of the source/drain underlies the gate.
The invention also provides a method of reading a selected memory cell in a ferroelectric memory, the memory including a plurality of memory cells arranged in rows and at least one column, each the cell containing a ferroelectric electronic component having a first electrical element and a second electrical element; the memory including a first conducting line associated with the column, each the first electrical element in the plurality of memory cells connected to the conducting line, the method comprising: placing the second electrical element in the memory cells in the row in which the selected cell is located in a first electronic state, and placing the second element of the cells in the non-selected rows in a second electronic state different from the first electronic state; connecting a current source to the first conducting line; determining the current flow from the current source into the first conducting line; and providing a data output signal representative of the logic state of the selected memory cell and depending on the current flow in the column select line. Preferably, the current flow is represents a first logic state if it is an essentially zero current flow and represents a second logic state if it is a non-zero current flow. Preferably, the ferroelectric electronic component is a ferroelectric FET having a source and a drain, the first electrical element is the drain of the FET, and the second electrical element is the source of the FET, although, alternatively, the first electrical element is the source of the FET, and the second electrical element is the drain of the FET. Preferably, the second electronic state is a resistance state and the first electronic state is a voltage state. Preferably, the first electronic state is the ground voltage state, and the second electronic state is a resistance state of at least one gigaohm.
The invention further provides a method of reading a selected memory cell in a ferroelectric memory, the memory including a plurality of memory cells arranged in rows and at least one column, each the cell containing a ferroelectric FET having a first electrical element and a second electrical element; the memory including a column select line associated with the column and a plurality of row select lines, each the row select line associated with one of the rows, each the first electrical element in the plurality of memory cells connected to the column select line, and each the second electrical element in the plurality of memory cells connected to its associated row select line, the method comprising: placing the column select line in a first electronic state; placing the row select line associated with the selected memory cell in a second electronic state different than the first electronic state; placing the row select lines not associated with the selected memory cell in a third electronic state different from the first and second electronic state; and providing a data output signal representative of the logic state of the selected memory cell and depending on the current flow in the column select line. Preferably, there are a plurality of the column select lines, the step of placing the column select line comprises placing each of the column select lines in the first electronic state, and the step of providing comprises simultaneously providing a data output signals representative of the logic states in a plurality of the selected memory cells. Preferably, the current flow represents a first logic state if it is an essentially zero current flow and represents a second logic state if it is a non-zero current flow. Preferably, the current flow represents a first logic state if it is a first current flow and represents a second logic state if it is a second current flow higher than the first current flow. Preferably, the third electronic state is a high resistance or floating state. Preferably, the ferroelectric FET has a source and a drain, the first electrical element is the drain, and the second electrical element is the source, although, alternatively, the first electrical element is the source, and the second electrical element is the drain. Preferably, the first and second electronic states are voltage states. Preferably, the second electronic state is the ground voltage state, and the third electronic state is a resistance state of at least one gigaohm. Preferably, the memory further includes a second conducting line associated with the column, the ferroelectric FET includes a third electrical element, and each the third electrical element in the plurality of memory cells is connected to the second conducting line, and wherein the method further includes the step of placing the second conducting line in an high resistance or open state. Preferably, the ferroelectric electronic component is a ferroelectric FET having a gate and the third electrical element is the gate of the FET.
In another aspect, the invention provides a method of reading a selected memory cell in a ferroelectric memory, the memory including a plurality of memory cells arranged in rows and columns, each the cell containing a ferroelectric FET having a gate electrode, a first source/drain, and a second source/drain, the method comprising: placing all of the gate electrodes in a gate electronic state; and reading the selected memory cell by determining a first source/drain electronic state of the first source/drain of the selected memory cell. Preferably, the first source/drain electronic state is a current flow state and the step of reading comprises: outputting a first signal representative of a first logic state of the selected memory cell if the current flow is a first current flow, and outputting a second signal representative of a second logic state of the selected memory cell if the current flow is a second current flow. Preferably, the second source/drain is a source, and the step of reading comprises applying a first voltage to each the source in the memory cells in the same row as the selected memory cell and applying a second voltage to each the source not in the selected row. Preferably, the gate electronic state is a high resistance electronic state, most preferably at least one gigaohm resistance.
The invention also provides a method of operating a ferroelectric memory including a plurality of memory cells, each the memory cell comprising a ferroelectric FET having a first source/drain, a second source/drain and a substrate, the method comprising the steps of: selecting one or more of the memory cells; placing the first source/drain of the cells which are not selected in a high resistance or open state; and performing a step selected from the steps consisting of writing information to the selected cell and reading information in the selected cell. Preferably, the method further comprises the step of placing the second source/drain of the cells which are not selected in a high resistance or open state. Preferably, the method further comprises the step of placing the substrate of the cells which are not selected in a high resistance or open state. Preferably, the step of performing comprises writing information to the selected cell. Preferably, the step of performing comprises reading information in the selected cell. Preferably, the resistance state is at least one gigaohm resistance. Preferably, the step of selecting comprises selecting a row of the memory cells, or alternatively, selecting a byte of the memory cells.
In a further aspect, the invention provides a method of writing to a ferroelectric memory, the memory including a plurality of memory cells each containing a ferroelectric FET, the ferroelectric FETs arranged in an array comprising a row and a plurality of columns, the method comprising: setting all of the cells in the row to a first logic state; and writing a second logic state to a selected cell in the row. Preferably, the memory includes a row line associated with the row and a plurality of column select lines, each column select line associated with one of the columns, and the step of writing a second logic state comprises placing the row line in a first electronic state and placing the column line associated with the selected cell in a second electronic state different than the first electronic state. Preferably, the first and second electronic states are voltage states. Preferably, the array comprises a plurality of rows of memory cells, the step of setting comprises setting all of the cells in a selected row to the first logic state, and the step of writing comprises writing the second logic state to a selected cell in the selected row. Preferably, the memory includes a row select line associated with each of the rows, and a plurality of column select lines, each column select line associated with one of the columns, and the step of writing a second logic state comprises placing the row select line in the selected row in a first electronic state and placing the column line associated with the selected cell in a second electronic state different than the first electronic state. Preferably, the array comprises a plurality of rows of memory cells, the step of setting comprises setting all of the cells in all of the rows to the first logic state, and the step of writing comprises writing the second logic state to a selected cell in a selected row. Preferably, the memory includes a row select line associated with each of the rows, and a plurality of column select lines, each column select line associated with one of the columns, and the step of writing a second logic state comprises placing the row select line of the selected row in a first electronic state and placing the column lines associated with the selected cells in a second electronic state different than the first electronic state. Preferably, the first and second electronic states are voltage states. Preferably, the first electronic state is the ground or logic xe2x80x9c0xe2x80x9d voltage, and the second electronic state is the high or logic xe2x80x9c1xe2x80x9d voltage. Preferably, the column lines not associated with the selected cell are placed in the ground or logic xe2x80x9c0xe2x80x9d state during the step of writing a second logic state. Preferably, the step of writing the second logic state comprises writing to a plurality of the selected cells. Preferably, wherein the plurality of selected cells are written to simultaneously.
In yet another aspect, the invention provides a method of writing to a ferroelectric memory, the memory including a plurality of memory cells each containing a ferroelectric FET, the ferroelectric FETs arranged in an array comprising a plurality of rows and a plurality of columns, the memory further including a plurality of row select lines, each of the row select lines associated with one of the rows of the ferroelectric FETs, the method comprising: selecting one of the plurality of rows; and simultaneously writing data to a plurality of memory cells in the selected row.
In still a further aspect, the invention provides a method of fabricating a ferroelectric memory having a gate structure comprising one or more material layers, at least one of the layers including a ferroelectric material, the method comprising: providing a semiconducting substrate; fabricating a first layer of the gate structure on the substrate; and forming an active area adjacent to first layer utilizing a self-aligned process. Preferably, the step of forming comprises forming a source. Preferably, the step of forming comprises forming a drain. Preferably, the step of forming comprises the steps of: placing a dopant material on or in the substrate; and heating the substrate to drive the dopant material into the substrate. Preferably, the step of placing comprises a step selected from the group consisting of diffusion and ion implantation. Preferably, the step of placing comprises placing the dopant material on the substrate. Preferably, the first layer is a non-ferroelectric insulating layer, and further including the step of forming a second layer comprising the ferroelectric material over the first layer. Preferably, the method further includes the step of forming a conductive layer over the second layer. Preferably, the step of forming an active area is performed after the step of forming a conductive layer. Preferably, the conductive layer is platinum.